The present invention relates to digital frequency generation. In particular, it relates to a method and apparatus for the digital generation of a pulse stream having a desired frequency relative to a reference clock signal and the ratio of two integers. The method applies generally to integers whose ratio is not an integer. The digital frequency generation (DFG) as a device can be integrated onto a simple chip, without need for an off-chip filter.
A number of techniques are used to synthesize signals in the art of direct digital synthesis. Many of these techniques utilize an accumulator to access a sine wave look-up table stored in a memory, which in turn produces a sequence of values representing a sine wave at the desired frequency. Using a digital-to-analog converter (DAC), the sequence of sine wave values is converted to an analog voltage and then passed through a low-pass filter to produce an analog voltage sine wave signal with the desired output frequency. This form of direct digital synthesis provides accurate control of the generation of signals over a wide range of frequencies. Significant portions of its circuitry can be manufactured using integrated circuits. Jones discloses an example of this type of system in U.S. Pat. No. 3,958,191 and Kovalick et al. discloses an accumulator and lookup ROM in U.S. Pat. No. 5,084,681.
In spite of its many advantages, this first method of direct digital synthesis has drawbacks, including the need for a fast high-resolution DAC and a multi-pole low-pass filter requiring precision discrete components. Consequently, the DAC and filter add size and cost to a product because they usually require components external to other integrated circuits.
A second type of direct digital synthesis uses the accumulator carry signal and remainder value to generate an output frequency without requiring a lookup sine table and a low-pass filter. In U.S. Pat. No. 5,195,044, Wischermann discloses an example of this type of system, wherein the carry signal generates an output pulse after a delay that is computed from the value remaining in the accumulator when carry signals an overflow. Like the first type, this second type of system generates an output frequency with a desired fractional relationship to the input reference clock, and it also requires multi-pole filters with physical components external to an integrated circuit. This second type of circuit uses an approximation when computing the carry signal delay, which in turn reduces the accuracy of the output frequency.
An opportunity is apparent to develop alternative digital frequency generator (DFG) circuitry. Simplified circuitry without artifacts tied to the clock that drives the DFG is useful in a variety of tunable electronic devices.